Radiant Foam Rendering on a Graph Processor

TL;DR

This paper introduces a distributed, in-SRAM volumetric renderer for the Graphcore IPU, enabling efficient ray marching entirely from on-chip SRAM and achieving near-interactive rendering speeds for complex scenes.

Contribution

It presents the first fully in-SRAM distributed renderer for volumetric rendering on a many-core accelerator, optimizing data distribution and communication for irregular workloads.

Findings

Achieves ~1 fps at 640x480 resolution on complex scenes

Maintains scene data and ray state entirely in on-chip SRAM

Provides insights into bottlenecks for future distributed-memory accelerators

Abstract

Many emerging many-core accelerators replace a single large device memory with hundreds to thousands of lightweight cores, each owning only a small local SRAM and exchanging data via explicit on-chip communication. This organization offers high aggregate bandwidth, but it breaks a key assumption behind many volumetric rendering techniques: that rays can randomly access a large, unified scene representation. Rendering efficiently on such hardware therefore requires distributing both data and computation, keeping ray traversal mostly local, and structuring communication into predictable routes. We present a fully in-SRAM, distributed renderer for the Radiant Foam Voronoi-cell volumetric representation on the Graphcore Mk2 IPU(Intelligence Processing Unit), a many-core accelerator with tile-local SRAM and explicit inter-tile communication. Our system shards the scene across tiles and forwards rays between shards through a hierarchical routing overlay, enabling ray marching entirely from on-chip SRAM with predictable communication. On Mip-NeRF~360 scenes, the system attains near-interactive throughput of approximately 1 fps at 640x480 with image and depth map quality close to the original GPU-based Radiant Foam implementation, while keeping all scene data and ray state in on-chip SRAM. Beyond demonstrating feasibility, we analyze routing, memory, and scheduling bottlenecks that inform how future distributed-memory accelerators can better support irregular, data-movement-heavy rendering workloads.