DSP-Based Sub-Switching-Period Current-Limiting Control for Grid-Tied Inverter under Grid Faults

TL;DR

This paper introduces a novel sub-switching period control method for grid-tied inverters that limits current during grid faults, ensuring stable operation and fault ride-through capability without complex hardware.

Contribution

It proposes a real-time current-limiting control technique that adjusts PWM carrier signals within a switching period, compatible with standard digital processors.

Findings

Effective current limiting during grid faults demonstrated

Works with common digital signal processors without extra hardware

Validated under various voltage sag and phase jump conditions

Abstract

This paper presents a sub-switching period current-limiting control for a grid-tied inverter to prevent transient overcurrents during grid faults and enable seamless fault ride-through (FRT). Sudden grid-voltage disturbances, such as voltage sags or phase jumps, can induce large transient currents within a switching period, particularly at low switching frequencies. Upon disturbance detection, the proposed method immediately modifies the pulse-width modulation carrier, enabling continuous regulation of the inverter output current within a time much shorter than a switching period without interrupting current flow. The proposed method can be implemented on commonly used digital signal processors without requiring specialized analog or digital circuits or high-speed computing devices. Experimental results from a 2-level, 3-phase inverter switching at 3.6 kHz validate the effectiveness of the proposed method under symmetric and asymmetric voltage sags and phase jumps.