Optimizing Fault-tolerant Cat State Preparation

TL;DR

This paper introduces a resource-efficient, fault-tolerant method for preparing large cat states in quantum computing, achieving high fault distances with optimized circuit depth and size.

Contribution

It proposes a novel scheme for fault-tolerant cat state preparation using low-depth circuits and transversal CNOTs, improving resource efficiency at higher fault distances.

Findings

Achieves fault-tolerant preparation of $w$-qubit cat states up to fault distance 9.

Uses logarithmic circuit depth and linear CNOT count relative to qubit number.

Employs SMT solving and heuristic methods for wiring the transversal CNOTs.

Abstract

Cat states are an important resource for fault-tolerant quantum computing, where they serve as building blocks for a variety of fault-tolerant primitives. Consequently, the ability to prepare high-quality cat states at large fault distances is essential. While optimizations for low fault distances or small numbers of qubits exist, higher fault distances can be achieved via generalized constructions with potentially suboptimal circuit sizes. In this work, we propose a cat state preparation scheme based on preparing two cat states with low-depth circuits, followed by a transversal CNOT and measurement of one of the states. This scheme prepares $w$-qubit cat states fault-tolerantly up to fault distances of $9$ using $\lceil\log_2 w\rceil+1$ depth and at most $3w-2$ CNOTs and $2w$ qubits. We discuss that the combinatorially challenging aspect of this construction is the precise wiring of the transversal CNOT and propose three methods for finding these: two based on Satisfiability Modulo Theory solving and one heuristic search based on a local repair strategy. Numerical evaluations show that our circuits achieve a high fault-distance while requiring fewer resources as generalized constructions.