Wafer-scale High-k SrTiO3 Dielectrics with Rational Barrier-layer Design for Low Leakage and High Charge Density

TL;DR

This paper demonstrates that incorporating a thin barrier layer beneath SrTiO3 significantly reduces leakage currents and enables higher charge densities, advancing the design of high-k dielectric devices with wafer-scale integration.

Contribution

It introduces a rational barrier-layer design approach using hybrid molecular beam epitaxy to enhance SrTiO3 dielectrics, enabling higher charge densities and low leakage at wafer scale.

Findings

SiO2 barrier layer enables higher operating voltages and charge densities.

Barrier layers reduce leakage currents effectively.

Trade-off between dielectric constant and capacitance with SiO2 layer.

Abstract

High-k oxides such as SrTiO3 promise large capacitance, but their dielectric response is often limited by leakage currents due to reduced bandgaps. We show that introducing a thin barrier layer beneath SrTiO3 is a simple and effective way to suppress leakage and increase charge density. Using hybrid molecular beam epitaxy, we grew uniform SrTiO3 films on Nb:SrTiO3, CaSnO3/Nb:SrTiO3, and 2-inch SiO2/p-Si stacks to directly compare how different barrier layers influence device behavior. Both CaSnO3 and SiO2 reduce leakage, but the ultra-wide-bandgap SiO2 layer enables much higher operating voltages, yielding charge densities exceeding 5x10^13 cm^-2 at room temperature - more than a fivefold enhancement compared to devices without a barrier layer. This improvement comes with a predictable trade-off: the lower dielectric constant of SiO2 reduces overall capacitance, making its thickness an important design parameter. Together, these results demonstrate that rational barrier-layer engineering - including wafer-scale integration on Si - provides a clear pathway to achieving higher charge densities in SrTiO3-based dielectric devices.