Developments in superconducting erasure qubits for hardware-efficient quantum error correction

TL;DR

This paper reviews recent advances in superconducting erasure qubits, highlighting their potential for hardware-efficient quantum error correction and discussing theoretical, simulation, and experimental developments.

Contribution

It provides a comprehensive overview of superconducting erasure qubits, including recent theoretical, simulation, and hardware progress, and discusses open challenges for fault-tolerant quantum computing.

Findings

Recent theoretical models show high noise thresholds for erasure qubits.

Simulation results demonstrate improved error correction performance.

Hardware prototypes of dual-rail superconducting erasure qubits have been developed.

Abstract

Quantum computers are inherently noisy, and a crucial challenge for achieving large-scale, fault-tolerant quantum computing is to implement quantum error correction. A promising direction that has made rapid recent progress is to design hardware that has a specific noise profile, leading to a significantly higher threshold for noise with certain quantum error correcting codes. This Perspective focuses on erasure qubits, which enable hardware-efficient quantum error correction, by concatenating an inner code built-in to the hardware with an outer code. We focus on implementations of dual-rail encoded erasure qubits using superconducting qubits, giving an overview of recent developments in theory and simulation, and hardware demonstrators. We also discuss the differences between implementations; near-term applications using quantum error detection; and the open problems for developing this approach towards early fault-tolerant quantum computers.