Implementation of high-efficiency, lightweight residual spiking neural network processor based on field-programmable gate arrays
Hou Yue, Xiang Shuiying, Zou Tao, Huang Zhiquan, Shi Shangxuan, Guo Xingxing, Zhang Yahui, Zheng Ling, Hao Yue

TL;DR
This paper introduces a lightweight, high-efficiency residual spiking neural network processor on FPGA that combines algorithm and hardware co-design to optimize inference speed and energy efficiency, outperforming GPUs and existing SNNs.
Contribution
It presents a novel FPGA-based SNN processor using single-timestep training, network compression, and hardware optimization for enhanced efficiency and speed.
Findings
Achieves 87.11% accuracy on CIFAR-10
Inference time of 3.98 ms per image
Energy efficiency of 183.5 FPS/W
Abstract
With the development of hardware-optimized deployment of spiking neural networks (SNNs), SNN processors based on field-programmable gate arrays (FPGAs) have become a research hotspot due to their efficiency and flexibility. However, existing methods rely on multi-timestep training and reconfigurable computing architectures, which increases computational and memory overhead, thus reducing deployment efficiency. This work presents an efficient and lightweight residual SNN accelerator that combines algorithm and hardware co-design to optimize inference energy efficiency. In terms of the algorithm, we employ single-timesteps training, integrate grouped convolutions, and fuse batch normalization (BN) layers, thus compressing the network to only 0.69M parameters. Quantization-aware training (QAT) further constrains all parameters to 8-bit precision. In terms of hardware, the reuse of…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Advanced Neural Network Applications · Ferroelectric and Negative Capacitance Devices
