Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi

TL;DR
This paper introduces REAP-cache, a scheme to prevent read disturbance accumulation in STT-MRAM caches, significantly improving reliability with minimal area and energy overhead.
Contribution
It formulates the read disturbance accumulation problem and proposes REAP-cache to eliminate it, enhancing cache reliability without performance loss.
Findings
REAP-cache extends cache MTTF by 171 times.
It increases cache area by less than 1%.
Energy consumption rises by only 2.7%.
Abstract
Spin-Transfer Torque Magnetic RAM (STT-MRAM) as one of the most promising replacements for SRAMs in on-chip cache memories benefits from higher density and scalability, near-zero leakage power, and non-volatility, but its reliability is threatened by high read disturbance error rate. Error-Correcting Codes (ECCs) are conventionally suggested to overcome the read disturbance errors in STT-MRAM caches. By employing aggressive ECCs and checking out a cache block on every read access, a high level of cache reliability is achieved. However, to minimize the cache access time in modern processors, all blocks in the target cache set are simultaneously read in parallel for tags comparison operation and only the requested block is sent out, if any, after checking its ECC. These extra cache block reads without checking their ECCs until requesting the blocks by the processor cause the accumulation…
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Taxonomy
TopicsMagnetic properties of thin films · Parallel Computing and Optimization Techniques · Matrix Theory and Algorithms
