Bridging Finite Element and Molecular Dynamics for Non-Fourier Thermal Transport Near Nanoscale Hot Spot

TL;DR

This paper combines molecular dynamics and finite element methods to accurately model non-Fourier heat transfer near nanoscale hot spots in advanced transistors, improving thermal prediction and device reliability.

Contribution

It introduces a size-dependent effective thermal conductivity and a framework to incorporate non-Fourier effects into FEM simulations for hot-spot analysis.

Findings

FEM with bulk conductivity underestimates hot-spot temperature

A size-dependent 'best' conductivity improves FEM accuracy

Decomposition of thermal resistance into multiple physical contributions

Abstract

Nanoscale hot spots forming tens of nanometers beneath the gate in advanced FinFET and HEMT devices drive heat transport into a non-Fourier regime, challenging conventional (Fourier-based) finite-element (FEM) analyses and complicating future thermal-aware chip design. Molecular dynamics (MD) naturally captures ballistic transport and phonon nonequilibrium, but has not been applied to hot-spot problems due to computational cost. Here, we perform the first MD simulations of hot-spot heat transfer across ballistic-diffusive regimes and benchmark them against FEM. We find that FEM using bulk thermal conductivity $\kappa_0$ significantly underestimates hot-spot temperature, even when the channel thickness is ~10 times the phonon mean free path, indicating persistent non-Fourier effects. We introduce a size-dependent "best" conductivity, $\kappa_{\mathrm{best}}$, using which FEM can reproduce MD hot-spot temperatures with high fidelity. We further decompose the MD-extracted thermal resistance into: (i) diffusive spreading, (ii) cross-plane ballistic, (iii) heat-carrier selective heating, and (iv) residual 3D ballistic-spreading resistances, and quantify each contribution. The resulting framework offers a practical route to embed non-Fourier physics into FEM for hot-spot prediction, reliability assessment, and thermally aware design of next-generation transistors.