Synthesis of signal processing algorithms with constraints on minimal parallelism and memory space

TL;DR

This thesis presents novel signal-processing algorithms and implementation strategies optimized for minimal parallelism and memory usage, aiming to enhance energy efficiency in low-power hardware.

Contribution

It introduces new models, approximation methods, and scheduling algorithms that optimize energy consumption and resource utilization in signal processing hardware.

Findings

Developed a power/energy consumption model for CMOS logic.

Created integer-friendly approximation methods with accuracy guarantees.

Proposed conflict-free data placement and execution schedules for FFT.

Abstract

This thesis develops signal-processing algorithms and implementation schemes under constraints of minimal parallelism and memory space, with the goal of improving energy efficiency of low-power computing hardware. We propose (i) a power/energy consumption model for clocked CMOS logic that supports selecting optimal parallelism, (ii) integer-friendly approximation methods for elementary functions that reduce lookup-table size via constrained piecewise-polynomial (quasi-spline) constructions with accuracy guarantees, (iii) provably conflict-free data placement and execution order for mixed-radix streaming FFT on multi-bank and single-port memories, including a self-sorting FFT variant, and (iv) a parallelism/memory analysis of the fast Schur algorithm for superfast Toeplitz system solving, motivated by echo-cancellation workloads. The results provide constructive theorems, schedules, and design trade-offs enabling efficient specialized accelerators.