HLS4PC: A Parametrizable Framework For Accelerating Point-Based 3D Point Cloud Models on FPGA

TL;DR

This paper introduces HLS4PC, a flexible FPGA framework that accelerates point-based 3D point cloud models, achieving significant throughput improvements and model simplification with minimal accuracy loss.

Contribution

The paper presents a parameterizable FPGA-based acceleration framework and a compressed PointMLP-Lite model for efficient real-time 3D point cloud processing.

Findings

3.56x higher FPGA throughput compared to previous FPGA works

2.3x higher throughput than GPU implementations

22x higher throughput than CPU implementations

Abstract

Point-based 3D point cloud models employ computation and memory intensive mapping functions alongside NN layers for classification/segmentation, and are executed on server-grade GPUs. The sparse, and unstructured nature of 3D point cloud data leads to high memory and computational demand, hindering real-time performance in safety critical applications due to GPU under-utilization. To address this challenge, we present HLS4PC, a parameterizable HLS framework for FPGA acceleration. Our approach leverages FPGA parallelization and algorithmic optimizations to enable efficient fixed-point implementations of both mapping and NN functions. We explore several hardware-aware compression techniques on a state-of-the-art PointMLP-Elite model, including replacing FPS with URS, parameter quantization, layer fusion, and input-points pruning, yielding PointMLP-Lite, a 4x less complex variant with only 2% accuracy drop on ModelNet40. Secondly, we demonstrate that the FPGA acceleration of the PointMLP-Lite results in 3.56x higher throughput than previous works. Furthermore, our implementation achieves 2.3x and 22x higher throughput compared to the GPU and CPU implementations, respectively.