Power Side-Channel Analysis of the CVA6 RISC-V Core at the RTL Level Using VeriSide

TL;DR

This paper assesses the vulnerability of the CVA6 RISC-V core to power side-channel attacks at the RTL level, demonstrating significant leakage during AES encryption that can compromise security.

Contribution

It introduces VeriSide, an RTL-level power profiling framework, and shows how CPA can reveal security vulnerabilities early in the design process.

Findings

Significant power leakage during AES encryption on CVA6 core

Correlation Power Analysis enables key recovery

Highlights importance of RTL-level security assessments

Abstract

Security in modern RISC-V processors demands more than functional correctness: It requires resilience to side-channel attacks. This paper evaluates the vulnerability of the side channel of the CVA6 RISC-V core by analyzing software-based AES encryption uses an RTL-level power profiling framework called VeriSide. This work represents that this design's Correlation Power Analysis (CPA) reveals significant leakage, enabling key recovery. These findings underscore the importance of early-stage RTL assessments in shaping future secure RISC-V designs.