Channel-last gate-all-around nanosheet oxide semiconductor transistors

TL;DR

This paper introduces a novel channel-last gate-all-around transistor architecture with amorphous oxide-semiconductor channels, achieving high performance without post-deposition annealing, suitable for scalable 3D low-power electronics.

Contribution

It proposes a new channel-last design for gate-all-around transistors that prevents damage during dielectric deposition, enabling high-performance devices with atomic layer deposited channels.

Findings

High on-state current (>1 mA/μm) achieved

Low subthreshold swing (as low as 63 mV/dec) demonstrated

No post-deposition annealing required for optimal performance

Abstract

As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor architectures, such as gate-all-around nanosheets, the conventional channel-first process involves depositing dielectrics directly onto the channel. Atomic layer deposition of gate dielectrics on back-end-of-line compatible channel materials, such as amorphous oxide semiconductors, can induce defects or cause structural modifications that degrade electrical performance. While post-deposition annealing can partially repair this damage, it often degrades other device metrics. We report a novel channel-last concept that prevents such damage. Channel-last gate-all-around self-aligned transistors with amorphous oxide-semiconductor channels exhibit high on-state current ($>$ 1 mA/$\mu$m) and low subthreshold swing (minimum of 63 mV/dec) without the need for post-deposition processing. This approach offers a general, scalable pathway for transistors with atomic layer deposited channel materials, enabling the future of low-power three-dimensional electronics.