Hardware-Algorithm Co-Design for Hyperdimensional Computing Based on Memristive System-on-Chip

TL;DR

This paper presents a co-design of hardware and algorithms for hyperdimensional computing on memristive System-on-Chip, enabling energy-efficient AI processing suitable for edge devices with promising classification accuracy.

Contribution

It introduces a novel hardware-algorithm co-design framework combining memristive in-memory computing with hyperdimensional encoding techniques for AI applications.

Findings

Achieved 90.71% accuracy in language classification

Demonstrated energy-efficient implementation on memristive SoC

Validated the effectiveness of hardware-aware encoding methods

Abstract

Hyperdimensional computing (HDC), utilizing a parallel computing paradigm and efficient learning algorithm, is well-suited for resource-constrained artificial intelligence (AI) applications, such as in edge devices. In-memory computing (IMC) systems based on memristive devices complement this by offering energy-efficient hardware solutions. To harness the advantages of both memristive IMC hardware and HDC algorithms, we propose a hardware-algorithm co-design approach for implementing HDC on a memristive System-on-Chip (SoC). On the hardware side, we utilize the inherent randomness of memristive crossbar arrays for encoding and employ analog IMC for classification. At the algorithm level, we develop hardware-aware encoding techniques that map data features into hyperdimensional vectors, optimizing the classification process within the memristive SoC. Experimental results in hardware demonstrate 90.71% accuracy in the language classification task, highlighting the potential of our approach for achieving energy-efficient AI deployments on edge devices.