Binary Neural Network Implementation for Handwritten Digit Recognition on FPGA

TL;DR

This paper presents a custom Verilog implementation of a binary neural network accelerator on FPGA for handwritten digit recognition, achieving real-time performance and high accuracy with low power consumption.

Contribution

It introduces a fully custom HDL design for BNN inference on FPGA, demonstrating real-time digit recognition with high efficiency and transparency, without relying on high-level synthesis tools.

Findings

Achieves 84% accuracy on MNIST dataset

Operates at 80 MHz with low power consumption

Provides a fully open-source Verilog implementation

Abstract

Binary neural networks provide a promising solution for low-power, high-speed inference by replacing expensive floating-point operations with bitwise logic. This makes them well-suited for deployment on resource-constrained platforms such as FPGAs. In this study, we present a fully custom BNN inference accelerator for handwritten digit recognition, implemented entirely in Verilog without the use of high-level synthesis tools. The design targets the Xilinx Artix-7 FPGA and achieves real-time classification at 80\,MHz with low power consumption and predictable timing. Simulation results demonstrate 84\% accuracy on the MNIST test set and highlight the advantages of manual HDL design for transparent, efficient, and flexible BNN deployment in embedded systems. The complete project including training scripts and Verilog source code are available at GitHub repo for reproducibility and future development.