LOCO: A Low-Cost SNU-Self-Resilient Latch Using an Output-Split C-Element

TL;DR

This paper introduces LOCO, a low-cost, self-resilient latch design that uses a novel Output-Split C-element to protect against soft errors with significantly reduced overhead and improved stability.

Contribution

It proposes a new Output-Split C-element and a low-cost SNU-resilient latch design that enhances soft error protection while reducing power, delay, and transistor count.

Findings

Achieves 19% fewer transistors compared to state-of-the-art designs.

Reduces power consumption by 63.58%.

Lowers delay by 74%.

Abstract

As the CMOS technology enters nanometer scales, integrated circuits (ICs) become increasingly sensitive to radiation-induced soft errors, which can corrupt the state of storage elements and cause severe reliability issues. Many hardened designs have been proposed to mitigate soft errors by using filtering elements. However, existing filtering elements only protect their inputs against soft errors and leave their outputs unprotected. Therefore, additional filtering elements must be added to protect outputs, resulting in extra overhead. In this paper, we first propose a novel Output-Split C-element (OSC) to protect both its input and output nodes, and then a novel LOw-COst single-node-upset (SNU) self-resilient latch (LOCO) to use OSCs to achieve both soft error resilience and low overhead. The usage of OSCs effectively reduce the short-circuit current of the LOCO latch during switching activities. Furthermore, the usage of clock gating and high-speed path reduces power consumption and delay, respectively. Compared with state-of-the-art SNU-resilient hardened designs, the LOCO latch achieves 19% fewer transistors, 63.58% lower power, 74% less delay, and 92% lower power-delay-product (PDP) on average. In addition, the LOCO latch exhibits better stability under variations in PVT (Process, Voltage, and Temperature).