A 14ns-Latency 9Gb/s 0.44mm$^2$ 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX

TL;DR

This paper introduces a low-latency, energy-efficient LDPC decoder ASIC for 5G URLLC, featuring a new short-blocklength LDPC code and fully parallel message-passing decoding to outperform existing solutions.

Contribution

It proposes a novel short-blocklength multi-rate LDPC code and a highly optimized ASIC decoder achieving record low latency and high throughput for URLLC applications.

Findings

Decoding latency of 14ns achieved

Throughput of 9Gb/s at 62pJ/b energy efficiency

Supports three rates with a 128-bit blocklength

Abstract

Ultra-reliable low latency communication (URLLC) is a key part of 5G wireless systems. Achieving low latency necessitates codes with short blocklengths for which polar codes with successive cancellation list (SCL) decoding typically outperform message-passing (MP)-based decoding of low-density parity-check (LDPC) codes. However, SCL decoders are known to exhibit high latency and poor area efficiency. In this paper, we propose a new short-blocklength multi-rate binary LDPC code that outperforms the 5G-LDPC code for the same blocklength and is suitable for URLLC applications using fully parallel MP. To demonstrate our code's efficacy, we present a 0.44mm$^2$ GlobalFoundries 22FDX LDPC decoder ASIC which supports three rates and achieves the lowest-in-class decoding latency of 14ns while reaching an information throughput of 9Gb/s at 62pJ/b energy efficiency for a rate-1/2 code with 128-bit blocklength.