SPIDER, a Waveform Digitizer ASIC for picosecond timing in LHCb PicoCal

TL;DR

SPIDER is a prototype waveform digitizer ASIC designed for picosecond timing in the LHCb Electromagnetic Calorimeter, featuring adjustable high-speed sampling and digital time reconstruction for fast detector readout.

Contribution

It introduces the first TSMC CMOS 65 nm ASIC prototype with a novel architecture for precise digital timing in high-energy physics detectors.

Findings

Achieved time resolution below 15 ps rms at >5 GeV

Implemented 2-20 GS/s adjustable sampling frequency

Demonstrated effective waveform digitization and digital time reconstruction

Abstract

We present the architecture, design and first test results of SPIDER, the first prototype of a TSMC CMOS 65 nm ASIC designed for the time measurement path of LHCb Electromagnetic Calorimeter after LS4 Upgrade. The main requirements for the readout of this detector are a time resolution below 15 ps rms above 5 GeV, and a channel occupancy up to 30\% (12 Mevent/s). The first prototype called SPIDER\_V0 is a 2-channel waveform digitizer locked on the LHC clock allowing precise time reconstruction by digital algorithms. The architecture is based on 2 DLLs in series controlling respectively the phase of the sampling window and the sampling frequency, the latter covering the range between 2 and 20 GS/s. Each self-triggering channel houses 8 banks of 32 analog memory cells and a massively parallel Wilkinson ADC for conversion at 5 GHz over 10 bits with a maximal conversion time of 200 ns. SPIDER targets not only LHCb, but all fast detectors mounted on current and future accelerators. Its sampling frequency can indeed be adjusted to different signal risetimes. Its main frequency of 40 MHz could even be eventually locked to another value by modifying only one of the DLLs in the chip design.