ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework

TL;DR

ReadyPower is a new analytical power model for processors that improves accuracy, reliability, and interpretability by incorporating multi-level parameters, outperforming ML-based models in experiments.

Contribution

It introduces ReadyPower, an analytical power modeling framework that addresses inaccuracies and interpretability issues of classical models by integrating multi-level parameters.

Findings

Achieves >20% lower MAPE than ML baselines

Provides >0.2 higher correlation coefficient R

Effective on multiple CPU architectures

Abstract

Power is a primary objective in modern processor design, requiring accurate yet efficient power modeling techniques. Architecture-level power models are necessary for early power optimization and design space exploration. However, classical analytical architecture-level power models (e.g., McPAT) suffer from significant inaccuracies. Emerging machine learning (ML)-based power models, despite their superior accuracy in research papers, are not widely adopted in the industry. In this work, we point out three inherent limitations of ML-based power models: unreliability, limited interpretability, and difficulty in usage. This work proposes a new analytical power modeling framework named ReadyPower, which is ready-for-use by being reliable, interpretable, and handy. We observe that the root cause of the low accuracy of classical analytical power models is the discrepancies between the real processor implementation and the processor's analytical model. To bridge the discrepancies, we introduce architecture-level, implementation-level, and technology-level parameters into the widely adopted McPAT analytical model to build ReadyPower. The parameters at three different levels are decided in different ways. In our experiment, averaged across different training scenarios, ReadyPower achieves >20% lower mean absolute percentage error (MAPE) and >0.2 higher correlation coefficient R compared with the ML-based baselines, on both BOOM and XiangShan CPU architectures.baselines, on both BOOM and XiangShan CPU architectures.