Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing

TL;DR

Lyra is a RISC-V verification framework that combines hardware acceleration with a semantic-aware generative model to produce high-quality stimuli, significantly improving coverage and verification speed over traditional fuzzers.

Contribution

Lyra introduces a heterogeneous FPGA-based verification system paired with LyraGen, a semantic-aware generative model, to enhance hardware verification efficiency and quality.

Findings

Achieves up to 1.27x higher coverage

Accelerates verification by up to 3343x

Demonstrates lower convergence difficulty

Abstract

As processor designs grow more complex, verification remains bottlenecked by slow software simulation and low-quality random test stimuli. Recent research has applied software fuzzers to hardware verification, but these rely on semantically blind random mutations that may generate shallow, low-quality stimuli unable to explore complex behaviors. These limitations result in slow coverage convergence and prohibitively high verification costs. In this paper, we present Lyra, a heterogeneous RISC-V verification framework that addresses both challenges by pairing hardware-accelerated verification with an ISA-aware generative model. Lyra executes the DUT and reference model concurrently on an FPGA SoC, enabling high-throughput differential checking and hardware-level coverage collection. Instead of creating verification stimuli randomly or through simple mutations, we train a domain-specialized generative model, LyraGen, with inherent semantic awareness to generate high-quality, semantically rich instruction sequences. Empirical results show Lyra achieves up to $1.27\times$ higher coverage and accelerates end-to-end verification by up to $107\times$ to $3343\times$ compared to state-of-the-art software fuzzers, while consistently demonstrating lower convergence difficulty.