EDAN: Towards Understanding Memory Parallelism and Latency Sensitivity in HPC

TL;DR

EDAN is a novel analysis tool that uses runtime instruction traces to estimate memory latency sensitivity and parallelism in HPC applications, aiding system design and optimization.

Contribution

EDAN introduces a new method for analyzing memory latency sensitivity using execution DAGs derived from runtime traces, avoiding complex hardware or simulation.

Findings

Reveals intrinsic memory-level parallelism in HPC applications

Estimates theoretical performance bounds based on latency sensitivity

Analyzes impact of hardware configurations on application performance

Abstract

Resource disaggregation is a promising technique for improving the efficiency of large-scale computing systems. However, this comes at the cost of increased memory access latency due to the need to rely on the network fabric to transfer data between remote nodes. As such, it is crucial to ascertain an application's memory latency sensitivity to minimize the overall performance impact. Existing tools for measuring memory latency sensitivity often rely on custom ad-hoc hardware or cycle-accurate simulators, which can be inflexible and time-consuming. To address this, we present EDAN (Execution DAG Analyzer), a novel performance analysis tool that leverages an application's runtime instruction trace to generate its corresponding execution DAG. This approach allows us to estimate the latency sensitivity of sequential programs and investigate the impact of different hardware configurations. EDAN not only provides us with the capability of calculating the theoretical bounds for performance metrics, but it also helps us gain insight into the memory-level parallelism inherent to HPC applications. We apply EDAN to applications and benchmarks such as PolyBench, HPCG, and LULESH to unveil the characteristics of their intrinsic memory-level parallelism and latency sensitivity.