Bounded Dynamic Level Maintenance for Efficient Logic Optimization
Junfeng Liu, Qinghua Zhao, Liwei Ni, Jingren Wang, Biwei Xie, Xingquan Li, Bei Yu, Shuai Ma

TL;DR
This paper introduces a bounded algorithm for dynamic level maintenance in logic optimization, significantly improving efficiency and scalability in circuit design by reducing update complexity without sacrificing quality.
Contribution
It presents the first bounded algorithm for dynamic level maintenance in DAGs, achieving near-linear time complexity for iterative logic optimization.
Findings
Average 6.4× overall speedup in benchmarks
1074.8× speedup in level maintenance tasks
Maintains optimization quality without degradation
Abstract
Logic optimization constitutes a critical phase within the Electronic Design Automation (EDA) flow, essential for achieving desired circuit power, performance, and area (PPA) targets. These logic circuits are typically represented as Directed Acyclic Graphs (DAGs), where the structural depth, quantified by node level, critically correlates with timing performance. Modern optimization strategies frequently employ iterative, local transformation heuristics (\emph{e.g.,} \emph{rewrite}, \emph{refactor}) directly on this DAG structure. As optimization continuously modifies the graph locally, node levels require frequent dynamic updates to guide subsequent decisions. However, a significant gap exists: existing algorithms for incrementally updating node levels are unbounded to small changes. This leads to a total of worst complexity in for given local subgraphs $\{\Delta…
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Taxonomy
TopicsVLSI and FPGA Design Techniques · Low-power high-performance VLSI design · Formal Methods in Verification
