Scalable IP Mimicry: End-to-End Deceptive IP Blending to Overcome Rectification and Scale Limitations of IP Camouflage

TL;DR

This paper introduces scalable, end-to-end deceptive IP blending techniques that improve upon existing IP camouflage methods by reducing overhead and enhancing resistance to reverse engineering attacks.

Contribution

It presents a novel graph-matching algorithm and a DNAS-based NAND array model to overcome scalability and representation limitations in IP camouflage.

Findings

Models are resilient to SAT and GNN-RE attacks

Achieve scalable and efficient end-to-end IP deception

Reduce overhead compared to previous methods

Abstract

Semiconductor intellectual property (IP) theft incurs estimated annual losses ranging from $225 billion to $600 billion. Despite initiatives like the CHIPS Act, many semiconductor designs remain vulnerable to reverse engineering (RE). IP Camouflage is a recent breakthrough that expands beyond the logic gate hiding of traditional camouflage through "mimetic deception," where an entire module masquerades as a different IP. However, it faces key limitations: requires a high-overhead post-generation rectification step, is not easily scalable, and uses an AIG logic representation that is mismatched with standard RE analysis flows. This paper addresses these shortcommings by introducing two novel, end-to-end models. We propose a Graph-Matching algorithm to solve the representation problem and a DNAS-based NAND Array model to achieve scalability. To facilitate this, we also introduce a mimicry-aware partitioning method, enabling a divide-and-conquer approach for large-scale designs. Our results demonstrate that these models are resilient to SAT and GNN-RE attacks, providing efficient and scalable paths for end-to-end deceptive IP design.