Gate-controlled analog memcapacitance in LaAlO3/SrTiO3 interface-based devices

TL;DR

This paper presents a novel gate-controlled memcapacitor using LaAlO3/SrTiO3 interfaces, demonstrating reversible capacitance tuning, hysteresis control, and potential for neuromorphic applications.

Contribution

It introduces a new memcapacitor design based on oxide interfaces with low-voltage operation and tunable hysteresis, advancing the field of electronic memory devices.

Findings

Reversible tuning of capacitance with gate voltage.

Enlarged hysteresis window at zero bias.

Model accurately reproduces experimental behavior.

Abstract

Current memcapacitor implementations typically demand complex fabrication processes or depend on organic materials exhibiting poor environmental stability and reproducibility. Here, we demonstrate memcapacitor structures utilizing a quasi 2-dimensional electron gas, formed at the crystalline LaAlO3/SrTiO3 heterointerface, as electrodes and SiO2/SrTiO3 as dielectric layer. The observed memcapacitance originates from the charge localization in a lateral floating gate, while an applied gate voltage enables reversible tuning of the device capacitance. Furthermore, preprogrammed or erased gate biases enable controllable shifts of the capacitance hysteresis window toward positive or negative bias, leading to an enlarged capacitance gap at zero bias. A memcapacitor model developed for this system reproduces the main features of the experimental capacitance hysteresis, capturing the effects of charge fluctuations and dielectric frequency modulation within the oxide layer. The demonstrated low-voltage operation and gate tunability of oxide interface-based memcapacitors highlight their potential for power-efficient, capacitor-based neuromorphic and synaptic electronic architectures.