Pinball: A Cryogenic Predecoder for Surface Code Decoding Under Circuit-Level Noise

TL;DR

Pinball is a cryogenic CMOS-based predecoder for surface code quantum error correction that significantly improves accuracy, reduces power consumption, and enhances scalability in realistic circuit-level noise environments.

Contribution

This work introduces Pinball, a novel cryogenic CMOS predecoder design that accounts for circuit-level noise, achieving higher accuracy and efficiency than prior solutions.

Findings

Outperforms state-of-the-art cryogenic predecoder by nearly six orders of magnitude in logical error rate.

Reduces logical error rate by 32.58x and area by 5x compared to RT predecoder.

Supports up to 2,668 logical qubits within a 1.5 W power budget at d=21.

Abstract

Scaling fault tolerant quantum computers, especially cryogenic systems based on the surface code, to millions of qubits is challenging due to poorly-scaling data processing and power consumption overheads. One key hurdle is the design of real-time quantum error correction (QEC) decoders, which demands high data rates for error processing; this is particularly apparent in systems with cryogenic qubits and room temperature (RT) decoders. In response, cryogenic predecoding using lightweight logic has been proposed to handle sparse errors in the cryogenic domain. However, prior work only accounts for a subset of error sources in real-world quantum systems with limited accuracy, often degrading performance below useful levels in practical scenarios. Moreover, prior reliance on SFQ logic precludes detailed architecture-technology co-optimization. To address these limitations, this paper introduces Pinball, a comprehensive design in cryogenic CMOS of a QEC predecoder for the surface code tailored to realistic, circuit-level noise. By accounting for error generation and propagation through QEC circuits, our design achieves higher predecoding accuracy, outperforming logical error rates (LER) of the current state-of-the-art (SOTA) cryogenic predecoder by nearly six orders of magnitude. Remarkably, despite operating under much stricter power and area constraints, Pinball also reduces LER by 32.58x and 5x, respectively, compared to SOTA RT predecoder and RT ensemble configurations. By increasing cryogenic coverage, we also reduce syndrome bandwidth up to 3780.72x. Through co-design with 4 K-characterized 22nm FDSOI technology, we achieve peak power consumption under 0.56 mW. Voltage/frequency scaling and body biasing enable 22.2x lower typical power consumption, yielding up to 67.4x total energy savings. Assuming a 1.5 W 4 K power budget, our predecoder supports up to 2,668 logical qubits at d=21.