LLMs for Analog Circuit Design Continuum (ACDC)

TL;DR

This paper explores the use of Large Language Models for analog circuit design, highlighting their potential and current limitations in reliability, data representation, and generalization within engineering tasks.

Contribution

It provides an empirical analysis of LLMs' applicability to analog circuit design, emphasizing data representation impacts and model reliability challenges.

Findings

LLMs show promise but face reliability issues in design tasks.

Data format significantly affects model performance.

Models struggle to generalize to unseen circuit configurations.

Abstract

Large Language Models (LLMs) and transformer architectures have shown impressive reasoning and generation capabilities across diverse natural language tasks. However, their reliability and robustness in real-world engineering domains remain largely unexplored, limiting their practical utility in human-centric workflows. In this work, we investigate the applicability and consistency of LLMs for analog circuit design -- a task requiring domain-specific reasoning, adherence to physical constraints, and structured representations -- focusing on AI-assisted design where humans remain in the loop. We study how different data representations influence model behavior and compare smaller models (e.g., T5, GPT-2) with larger foundation models (e.g., Mistral-7B, GPT-oss-20B) under varying training conditions. Our results highlight key reliability challenges, including sensitivity to data format, instability in generated designs, and limited generalization to unseen circuit configurations. These findings provide early evidence on the limits and potential of LLMs as tools to enhance human capabilities in complex engineering tasks, offering insights into designing reliable, deployable foundation models for structured, real-world applications.