A Hybrid Residue Floating Numerical Architecture for High Precision Arithmetic on FPGAs

TL;DR

This paper introduces HRFNA, a novel hybrid arithmetic architecture for FPGAs that combines residue channels with floating point scaling, achieving high precision with improved throughput and reduced resource usage.

Contribution

The paper presents the first unified hybrid residue floating numerical architecture optimized for FPGA implementation, with detailed mathematical framework and microarchitectures.

Findings

Over 2.1x throughput improvement compared to IEEE 754 single precision

38-52% LUT reduction on FPGA

Maintains numerical stability in long iterative sequences

Abstract

Floating point arithmetic remains expensive on FPGA platforms due to wide datapaths and normalization logic, motivating alternative representations that preserve dynamic range at lower cost. This work introduces the Hybrid Residue Floating Numerical Architecture (HRFNA), a unified arithmetic system that combines carry free residue channels with a lightweight floating point scaling factor. We develop the full mathematical framework, derive bounded error normalization rules, and present FPGA optimized microarchitectures for modular multiplication, exponent management, and hybrid reconstruction. HRFNA is implemented on a Xilinx ZCU104, with Vitis simulation, RTL synthesis, and on chip ILA traces confirming cycle accurate correctness. The architecture achieves over 2.1 times throughput improvement and 38-52 percent LUT reduction compared to IEEE 754 single precision baselines while maintaining numerical stability across long iterative sequences. These results demonstrate that HRFNA offers an efficient and scalable alternative to floating point computation on modern FPGA devices.