Architecture Design for Rise/Fall Asymmetry Glitch Minimization in Current-Steering DACs

TL;DR

This paper proposes a new DAC architecture that minimizes output glitches caused by asymmetries in switch response, improving dynamic performance in high-speed applications like optical communications.

Contribution

It introduces a novel DAC weighting scheme based on a formulated glitch metric to reduce fall/rise asymmetry glitches in current-steering DACs.

Findings

Proposed architecture reduces output glitches significantly.

Numerical simulations demonstrate performance advantages over segmented structures.

New weighting scheme improves DAC dynamic performance.

Abstract

Current-steering digital-to-analog converter (DAC) is a prominent architecture that is commonly used in high-speed applications such as optical communications. One of the shortcomings of this architecture is the output glitches that are input dependent and degrade the dynamic performance of the DAC. We investigate DAC glitches that arise from asymmetry in the fall/rise response of DAC switches. We formulate a glitch metric that defines the overall DAC performance, which is then used to find a novel DAC weighting scheme. Numerical simulations show that the proposed architecture can potentially provide a significant performance advantage compared to the segmented structure.