Timing-Error Optimized Architecture for Current-Steering DACs

TL;DR

This paper introduces a new DAC architecture optimized to reduce timing mismatch distortion, along with algorithms for decoding input codes, demonstrating improved performance through simulations.

Contribution

The paper presents a novel timing-error optimized architecture for current-steering DACs and three decoding algorithms, enhancing dynamic performance.

Findings

Reduced distortion due to timing mismatch

Improved dynamic performance in simulations

Effective algorithms for code decoding

Abstract

We propose a novel digital-to-analog converter (DAC) weighting architecture that statistically minimizes the distortion caused by random timing mismatches among current sources. To decode the DAC input codewords into corresponding DAC switches, we present three algorithms with varying computational complexities. We perform high-level Matlab simulations to illustrate the dynamic performance improvement over the segmented structure.