1024-Channel 0.8V 23.9-nW/Channel Event-based Compute In-memory Neural Spike Detector
Ye Ke, Zhengnan Fu, Junyi Yang, Hongyang Shang, and Arindam Basu

TL;DR
This paper presents a highly efficient, low-power event-based spike detection macro for neural interfaces, enabling scalable, accurate neural spike detection with minimal energy consumption suitable for high-density brain-machine interfaces.
Contribution
Introduces a novel event-based spike detection algorithm and a low-power 10-T eDRAM-SRAM hybrid memory architecture for scalable neural spike detection in high-density iBMIs.
Findings
Achieved 96.06% spike detection accuracy on synthetic data
Attained 95.08% similarity and 0.05 MAE on Neuropixel recordings
Realized 23.9 nW per channel energy efficiency and 375 um^2 area per channel
Abstract
The increasing data rate has become a major issue confronting next-generation intracortical brain-machine interfaces (iBMIs). The scaling number of recording sites requires complex analog wiring and lead to huge digitization power consumption. Compressive event-based neural frontends have been used in high-density neural implants to support the simultaneous recording of more channels. Event-based frontends (EBF) convert recorded signals into asynchronous digital events via delta modulation and can inherently achieve considerable compression. But EBFs are prone to false events that do not correspond to neural spikes. Spike detection (SPD) is a key process in the iBMI pipeline to detect neural spikes and further reduce the data rate. However, conventional digital SPD suffers from the increasing buffer size and frequent memory access power, and conventional spike emphasizers are not…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · EEG and Brain-Computer Interfaces · Neural dynamics and brain function
