Enhancing Hole Mobility in Monolayer $WSe_{2}$ p-FETs via Process-Induced Compression

TL;DR

This study demonstrates that applying biaxial compression to monolayer WSe2 p-FETs significantly enhances hole mobility and on-current, primarily by reducing inter-valley scattering, with effects confirmed through combined experimental and simulation approaches.

Contribution

The paper introduces a process-induced compression method to improve hole mobility in monolayer WSe2 p-FETs, supported by experimental measurements and simulations showing substantial performance enhancements.

Findings

Hole mobility increases at 340% per % strain

On-current increases at 460% per % strain

Compression reduces inter-valley scattering in WSe2

Abstract

Understanding the interactions between strain, interfacial mechanics, and electrical performance is critical for designing beyond silicon electronics based on hetero-integrated 2D materials. Through combined experiment and simulation, we demonstrated and analyzed the enhancement of hole mobility in p-type monolayer $WSe_{2}$ field effect transistors (FETs) under biaxial compression. We tracked FET performance versus strain by incrementing compressive strain to $WSe_{2}$ channels via sequential AlOx deposition and performing intermediate photoluminescence and transport measurements. The hole mobility factor increased at a rate of 340 $\pm$ 95 %/%$\epsilon$, and the on-current factor increased at a rate of 460 $\pm$ 340 %/%$\epsilon$. Simulation revealed that the enhancement under compression arises primarily from a reduction in inter-valley scattering between the $\Gamma$--K valence bands, and the rate is robust against variations in carrier density, impurity density, or dielectric environment. These findings show that compressive strain is a powerful technique for enhancing performance in 2D p-FETs and that it is multiplicative with defect and doping engineering.