Efficient and Accurate Graph Classification with Hyperdimensional Computing on FPGA

TL;DR

This paper introduces HyperX, an FPGA-based accelerator for Nyström-based hyperdimensional computing in graph classification, achieving significant speed and energy efficiency improvements while enhancing accuracy on edge devices.

Contribution

HyperX is the first end-to-end FPGA accelerator for Nyström-based HDC graph classification, integrating novel optimizations for improved accuracy and resource efficiency.

Findings

Achieves 6.85x speedup over CPU and 4.32x over GPU.

Provides 169x energy efficiency gain over CPU and 314x over GPU.

Improves classification accuracy by 3.4% on average across benchmarks.

Abstract

Real-time, energy-efficient inference on edge devices is essential for graph classification across a range of applications. Hyperdimensional Computing (HDC) is a brain-inspired computing paradigm that encodes input features into low-precision, high-dimensional vectors with simple element-wise operations, making it well-suited for resource-constrained edge platforms. Recent work enhances HDC accuracy for graph classification via Nystr\"om kernel approximations. Edge acceleration of such methods faces several challenges: (i) redundancy among (landmark) samples selected via uniform sampling, (ii) storing the Nystr\"om projection matrix under limited on-chip memory, (iii) expensive, contention-prone codebook lookups, and (iv) load imbalance due to irregular sparsity in SpMV. To address these challenges, we propose HyperX, the first end-to-end FPGA accelerator for Nystr\"om-based HDC graph classification at the edge. HyperX integrates four key optimizations: (i) a hybrid landmark selection strategy combining uniform sampling with determinantal point processes (DPPs) to reduce redundancy while improving accuracy; (ii) a streaming architecture for Nystr\"om projection matrix maximizing external memory bandwidth utilization; (iii) a minimal-perfect-hash lookup engine enabling $O(1)$ key-to-index mapping; and (iv) sparsity-aware SpMV engines with static load balancing. Implemented on an AMD Zynq UltraScale+ (ZCU104) FPGA, HyperX achieves $6.85\times$ ($4.32\times$) speedup and $169\times$ ($314\times$) energy efficiency gains over optimized CPU (GPU) baselines, while improving classification accuracy by $3.4\%$ on average across TUDataset benchmarks, a widely used standard for graph classification.