Artificial Intelligence-Driven Network-on-Chip Design Space Exploration: Neural Network Architectures for Design

TL;DR

This paper introduces a machine learning framework that automates and accelerates Network-on-Chip design space exploration, improving prediction accuracy and significantly reducing exploration time using neural network models and simulation data.

Contribution

It compares three neural network architectures for predicting optimal NoC parameters, highlighting the effectiveness of the Conditional Diffusion Model in this context.

Findings

Conditional Diffusion Model achieved MSE of 0.463

Framework generated over 150,000 simulation data points

Design exploration time reduced by several orders of magnitude

Abstract

Network-on-Chip (NoC) design requires exploring a high-dimensional configuration space to satisfy stringent throughput requirements and latency constraints. Traditional design space exploration techniques are often slow and struggle to handle complex, non-linear parameter interactions. This work presents a machine learning-driven framework that automates NoC design space exploration using BookSim simulations and reverse neural network models. Specifically, we compare three architectures - a Multi-Layer Perceptron (MLP),a Conditional Diffusion Model, and a Conditional Variational Autoencoder (CVAE) to predict optimal NoC parameters given target performance metrics. Our pipeline generates over 150,000 simulation data points across varied mesh topologies. The Conditional Diffusion Model achieved the highest predictive accuracy, attaining a mean squared error (MSE) of 0.463 on unseen data. Furthermore, the proposed framework reduces design exploration time by several orders of magnitude, making it a practical solution for rapid and scalable NoC co-design.