A manufacturable surface code architecture for spin qubits with fast transversal logic

TL;DR

This paper proposes the SNAQ surface code architecture for spin qubits in silicon, leveraging rapid qubit shuttling to enable dense layouts and fast transversal logic, significantly improving fault-tolerant quantum computation efficiency.

Contribution

It introduces the SNAQ architecture that relaxes readout constraints using spin shuttling, enabling dense qubit layouts and fast logical operations in silicon-based spin qubit arrays.

Findings

Orders-of-magnitude reduction in chip area per logical qubit.

Over 10x improvement in local logical clock speed.

3.2-5.7x improvement in fault-tolerant subroutines.

Abstract

Spin qubits in silicon quantum dot arrays are a promising quantum computation platform for long-term scalability due to their small qubit footprint and compatibility with advanced semiconductor manufacturing. However, spin qubit devices face a key architectural bottleneck: the large physical footprint of readout components relative to qubits prevents a dense layout where all qubits can be measured simultaneously, complicating the implementation of quantum error correction. This challenge is offset by the platform's unique rapid shuttling capability, which can be used to transport qubits to distant readout ports. In this work, we explore the design constraints and capabilities of spin qubits in silicon and propose the SNAQ (Shuttling-capable Narrow Array of spin Qubits) surface code architecture, which relaxes the 1:1 readout-to-qubit assumption by leveraging spin shuttling to time-multiplex ancilla qubit initialization and readout. Our analysis shows that, given sufficiently high (experimentally demonstrated) qubit coherence times, SNAQ delivers an orders-of-magnitude reduction in chip area per logical qubit. Additionally, by using a denser grid of physical qubits, SNAQ enables fast transversal logic for short-distance logical operations, achieving over 10x improvement in local logical clock speed while still supporting global operations via lattice surgery. This translates to a 3.2-5.7x improvement in key Adder and Lookup fault-tolerant subroutines. Our work pinpoints critical hardware metrics and provides a compelling path toward high-performance fault-tolerant computation on near-term-manufacturable spin qubit arrays.