BitStopper: An Efficient Transformer Attention Accelerator via Stage-fusion and Early Termination
Huizheng Wang, Hongbin Wang, Shaojun Wei, Yang Hu, Shouyi Yin

TL;DR
BitStopper introduces a novel transformer attention acceleration method that combines stage-fusion and early termination techniques, significantly reducing computation and memory costs in large language models.
Contribution
It presents a new hardware-efficient algorithm-architecture co-design that eliminates the need for a sparsity predictor and enhances performance through stage fusion and adaptive token selection.
Findings
Achieves over 2x speedup compared to state-of-the-art accelerators.
Delivers more than 2x improvements in energy efficiency.
Effectively reduces memory access and computation in transformer models.
Abstract
Attention-based large language models (LLMs) have transformed modern AI applications, but the quadratic cost of self-attention imposes significant compute and memory overhead. Dynamic sparsity (DS) attention mitigates this, yet its hardware efficiency is limited by the added prediction stage and the heavy memory traffic it entails. To address these limitations, this paper proposes BitStopper, a fine-grained algorithm-architecture co-design that operates without a sparsity predictor. First, a bit-serial enable stage fusion (BESF) mechanism is proposed to reuse and minimize the memory access by progressively terminating trivial tokens and merging the prediction stage into the execution stage. Second, a lightweight and adaptive token selection (LATS) strategy is developed to work in concert with the bit-level sparsity speculation. Third, a bit-level asynchronous processing (BAP) strategy…
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Advanced Neural Network Applications · Low-power high-performance VLSI design
