A 33.6-136.2 TOPS/W Nonlinear Analog Computing-In-Memory Macro for Multi-bit LSTM Accelerator in 65 nm CMOS
Junyi Yang, Xinyu Luo, Ye Ke, Zheng Wang, Hongyang Shang, Shuai Dong, Zhengnan Fu, Xiaofeng Yang, Hongjie Liu, Arindam Basu

TL;DR
This paper introduces a highly energy-efficient analog in-memory macro for LSTM accelerators, enabling direct nonlinear activation computation with high accuracy and robustness, significantly improving energy and area efficiency over existing solutions.
Contribution
It presents a novel nonlinear in-memory ADC and macro design for LSTM accelerators, achieving high energy efficiency and accuracy in analog computing-in-memory architectures.
Findings
Achieves 92.0% inference accuracy on keyword spotting
Demonstrates 2.2X higher energy efficiency than state-of-the-art
Shows robustness of ADC against temperature variations
Abstract
The energy efficiency of analog computing-in-memory (ACIM) accelerator for recurrent neural networks, particularly long short-term memory (LSTM) network, is limited by the high proportion of nonlinear (NL) operations typically executed digitally. To address this, we propose an LSTM accelerator incorporating an ACIM macro with reconfigurable (1-5 bit) nonlinear in-memory (NLIM) analog-to-digital converter (ADC) to compute NL activations directly in the analog domain using: 1) a dual 9T bitcell with decoupled read/write paths for signed inputs and ternary weight operations; 2) a read-word-line underdrive Cascode (RUDC) technique achieving 2.8X higher read-bitline dynamic range than single-transistor designs (1.4X better over conventional Cascode structure with 7X lower current variation); 3) a dual-supply 6T-SRAM array for efficient multi-bit weight operations and reducing both bitcell…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · Neural Networks and Reservoir Computing
