From PyTorch to Calyx: An Open-Source Compiler Toolchain for ML Accelerators

TL;DR

This paper introduces an open-source compiler toolchain that translates PyTorch ML models into synthesizable hardware designs using Calyx, enabling FPGA deployment with competitive performance.

Contribution

It presents a novel open-source compiler pipeline from PyTorch to hardware, integrating Allo, Calyx, and CIRCT for efficient FPGA design.

Findings

Generated FPGA hardware designs with competitive performance.

Implemented memory partitioning passes for parallelism.

Demonstrated effectiveness against industry tools like Vitis HLS.

Abstract

We present an end-to-end open-source compiler toolchain that targets synthesizable SystemVerilog from ML models written in PyTorch. Our toolchain leverages the accelerator design language Allo, the hardware intermediate representation (IR) Calyx, and the CIRCT project under LLVM. We also implement a set of compiler passes for memory partitioning, enabling effective parallelism in memory-intensive ML workloads. Experimental results demonstrate that our compiler can effectively generate optimized FPGA-implementable hardware designs that perform reasonably well against closed-source industry-grade tools such as Vitis HLS.