Using Open Source EDA Tools in ASICs for HEP: A Mixed Comparison

TL;DR

This paper evaluates open-source EDA tools against commercial ones for ASIC design in high-energy physics, highlighting their relative strengths and limitations in digital and analog circuit implementations.

Contribution

It provides a detailed comparison of open-source and commercial EDA tools on multiple circuit blocks within the IHP 130 nm open PDK, including quantitative analysis of design effort and quality.

Findings

Open-source tools are viable for early prototyping and training.

Commercial tools achieve better area, power, and layout quality.

Open-source tools show increased design effort and larger area/power in some cases.

Abstract

This work compares open-source electronic design automation tools with a commercial environment using three representative integrated circuit blocks in the IHP 130 nm open PDK: a common-mode noise filter, a finite-state machine, and a voltage-controlled oscillator. The study reports design effort and quality of results for digital logic, including area, power, and timing closure, and examines analog layout feasibility. For the finite-state machine at 50 MHz, the open-source flow reached 0.029 mm$^2$ (post-layout) and 4.37 mW (estimated) with 828 standard cells, whereas the commercial flow achieved 0.019 mm$^2$ and 2.00 mW with 497 cells, corresponding to increases of 53\% in area and 118\% in power. The common-mode noise filter totals 1.879 mm$^2$ with 1703 flip-flops at 50 MHz. The voltage-controlled oscillator occupies 0.0025 mm$^2$ and achieves a simulated maximum oscillation frequency of 2.65 GHz. The contribution is a side-by-side quantification of quality of results across digital and analog blocks in the IHP open PDK. The results indicate that open-source tools are viable for early prototyping, training, and collaboration, while commercial flows retain advantages in automation and quality of results when strict targets on power and area or precision analog layout are required.