Highly resilient, error-protected quantum gates in a solid-state quantum network node

TL;DR

This paper demonstrates error-protected quantum gates in a solid-state quantum network node, achieving record low error rates and high fidelity, crucial for fault-tolerant quantum computing and communication.

Contribution

The work introduces PUDDINGs, a new class of composite pulses that enhance robustness of quantum gates against frequency and amplitude errors, with experimental validation in NV centers.

Findings

Error per gate improved up to a factor of 9

Achieved two-qubit gate error of 1.2 x 10^-5

Fidelity of 99.9988% at cryogenic temperatures

Abstract

High-fidelity quantum gates are a cornerstone of any quantum computing and communications architecture. Realizing such control in the presence of realistic errors at the level required for beyond-threshold quantum error correction is a long-standing challenge for all quantum hardware platforms. Here we theoretically develop and experimentally demonstrate error-protected quantum gates in a solid-state quantum network node. Our work combines room-temperature randomized benchmarking with a new class of composite pulses that are simultaneously robust to frequency and amplitude, affecting random and systematic errors. We introduce Power-Unaffected, Doubly-Detuning-Insensitive Gates (PUDDINGs) -- a theoretical framework for constructing conditional gates with immunity to both amplitude and frequency errors. For single-qubit and two-qubit CNOT gate demonstrations in a solid-state nitrogen-vacancy (NV) center in diamond, we systematically measure an improvement in the error per gate up to a factor of 9. By projecting the application of PUDDING to cryogenic temperatures we show a record two-qubit error per gate of $1.2 \times 10^{-5}$, corresponding to a fidelity of $99.9988\%$, far below the thresholds required by surface and color code error correction. These results present viable building blocks for a new class of fault-tolerant quantum networks and represent the first experimental realization of error-protected conditional gates in solid-state systems.