FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration

TL;DR

FLEX is a novel FPGA-CPU accelerator that significantly speeds up mixed-cell-height legalization tasks in chip design by optimizing task partitioning, employing multi-granularity pipelining, and enhancing cell shifting processes, outperforming existing solutions.

Contribution

This work introduces FLEX, combining FPGA and CPU for legalization acceleration with innovative task assignment and pipelining techniques, achieving substantial speedups and improved quality.

Findings

Up to 18.3x speedup over CPU-GPU legalizers

Up to 5.4x speedup over multi-threaded CPU legalizers

Legalization quality improved by 4% and 1%

Abstract

In this work, we present FLEX, an FPGA-CPU accelerator for mixed-cell-height legalization tasks. We address challenges from the following perspectives. First, we optimize the task assignment strategy and perform an efficient task partition between FPGA and CPU to exploit their complementary strengths. Second, a multi-granularity pipelining technique is employed to accelerate the most time-consuming step, finding optimal placement position (FOP), in legalization. At last, we particularly target the computationally intensive cell shifting process in FOP, optimizing the design to align it seamlessly with the multi-granularity pipelining framework for further speedup. Experimental results show that FLEX achieves up to 18.3x and 5.4x speedups compared to state-of-the-art CPU-GPU and multi-threaded CPU legalizers with better scalability, while improving legalization quality by 4% and 1%.