A CMOS+X Spiking Neuron With On-Chip Machine Learning

TL;DR

This paper introduces a CMOS+X spiking neuron design with integrated on-chip learning, capable of mimicking biological neuron behaviors and supporting neural network training in a compact, low-power hardware platform.

Contribution

It presents a novel CMOS+X neuron architecture with intrinsic learning capabilities, simulated in LTspice, demonstrating biological functionalities and effective training in an analog neuromorphic network.

Findings

Neuron model reproduces biological behaviors without extra circuitry

Network successfully learns a nonlinear task

Demonstrates potential for low-power neuromorphic hardware

Abstract

We present the design and numerical simulation of a spiking neuron capable of on-chip machine learning. Built within the CMOS+X framework, the spiking neuron consists of an NMOS transistor combined with a magnetic tunnel junction (MTJ). This NMOS+MTJ unit, when simulated in the industry-standard circuit simulation software LTspice, reproduces multiple functions of a biological neuron, including threshold spiking, latency, refractory periods, synaptic integration, inhibition, and adaptation. These behaviors arise from the intrinsic magnetization dynamics of the MTJ and do not require any additional control circuitry. By interconnecting the NMOS+MTJ neurons, we construct a model of an analog multilayer network that learns through spike-timing-dependent weight updates derived from a gradient-descent rule, with both training and inference modeled in the analog domain. The simulated CMOS+X network achieves reliable spike propagation and successful training on a nonlinear task, indicating a feasible path toward compact, low-power, in-memory neuromorphic hardware for edge applications.