The BrainScaleS-2 multi-chip system: Interconnecting continuous-time neuromorphic compute substrates

TL;DR

This paper presents the design and scaling of the BrainScaleS-2 neuromorphic system, integrating analog and digital components with FPGA-based interconnections, achieving low-latency chip-to-chip communication within a modular rack setup.

Contribution

It introduces FPGA-based interconnection architecture for BrainScaleS-2, enabling scalable multi-chip neuromorphic systems with low latency.

Findings

Achieved chip-to-chip latencies below 1.3 microseconds across three FPGAs.

Developed a scalable FPGA-based interconnection architecture for neuromorphic systems.

Integrated multiple backplanes into a standard rack case for modular expansion.

Abstract

The BrainScaleS-2 SoC integrates analog neuron and synapse circuits with digital periphery, including two CPUs with SIMD extensions. Each ASIC is connected to a Node-FPGA, providing experiment control and Ethernet connectivity. This work details the scaling of the compute substrate through FPGA-based interconnection via an additional Aggregator unit. The Aggregator provides up to 12 transceiver links to a backplane of Node-FPGAs, as well as 4 transceiver lanes for further extension. Two such interconnected backplanes are integrated into a standard 19in rack case with 4U height together with an Ethernet switch, system controller and power supplies. For all spike rates, chip-to-chip latencies -- consisting of four hops across three FPGAs -- below 1.3$\mu$s are achieved within each backplane.