A Space-Charge-Limited van der Waals Spin Transistor

TL;DR

This paper introduces a novel 2D antiferromagnetic spin transistor using CrSBr that combines space-charge-limited conduction with magnetic control, enabling multilevel memristive states and advancing 2D magnetic semiconductor applications.

Contribution

It demonstrates a new spin transistor concept integrating vertical and lateral transport in 2D magnetic semiconductors with gate-tunable magnetoresistance and memristive behavior.

Findings

Giant, gate-tunable magnetoresistance observed.

Visualization of layer-sharing effects influencing spin states.

Multilevel conductance states enabled by magnetic switching.

Abstract

Integrating semiconducting and magnetic materials could combine transistor-like operation with nonvolatility and enable architectures such as logic-in-memory. Here, we employ correlated electrical transport and scanning nitrogen-vacancy (NV) center magnetic imaging to elucidate a spin transistor concept that amalgamates both vertical and lateral transport in a 2D antiferromagnetic semiconductor, distinct from purely vertical tunneling devices. Our device, based on a monolayer-bilayer junction in CrSBr, displays giant, gate-tunable magnetoresistance driven by the dual action of electrostatic doping on space-charge-limited lateral conduction and interlayer exchange coupling. Moreover, we visualize a field-trainable, layer-sharing effect that selects between coherent or domain-wall reversal at the spin-flip transition, enabling multilevel, memristive conductance states. These findings open opportunities for 2D magnetic semiconductors to address limitations in contemporary computing.