Accurate Modeling of Gate Leakage Currents in SiC Power MOSFETs

TL;DR

This paper presents a comprehensive physics-based simulation framework for accurately modeling gate leakage currents in SiC MOSFETs, capturing complex coupled processes without empirical fitting across wide temperature and bias ranges.

Contribution

The authors develop a self-consistent, physics-based model that integrates electrostatics, quantum tunneling, and impact ionization, providing predictive insights into gate leakage mechanisms in SiC MOSFETs.

Findings

Model accurately reproduces measured gate-current-voltage characteristics.

Impact ionization triggered by conduction electrons enhances gate leakage.

Framework applies across wide temperature and bias ranges.

Abstract

Silicon carbide (SiC) metal-oxide-semiconductor field-effect-transistors (MOSFETs) enable high-voltage and high-temperature power conversion. Compared to Si devices, they suffer from pronounced gate leakage due to the reduced electron tunneling barrier at the interface between SiC and amorphous silicon dioxide (a-SiO$_2$). We develop a self-consistent, physics-based simulation framework that couples electrostatics, quantum tunneling, carrier transport, impact ionization, and charge trapping for both electrons and holes. The model quantitatively reproduces measured gate-current-voltage characteristics of SiC MOS capacitors over a wide temperature (80-573 K) range and a wide bias range without empirical fitting. Simulations reveal that conduction electrons in a-SiO$_2$ can trigger impact ionization, which generates electron-hole pairs, and leads to capture of holes in the oxide bulk, thereby enhancing gate leakage current. The framework captures these coupled processes across multiple orders of magnitude in time and field, providing predictive capability for oxide reliability. Although demonstrated for SiC devices, the methodology also applies to Si technologies that uses the same gate dielectric.