Near-Memory Architecture for Threshold-Ordinal Surface-Based Corner Detection of Event Cameras
Hongyang Shang, An Guo, Shuai Dong, Junyi Yang, Ye Ke, Arindam Basu

TL;DR
This paper introduces a near-memory hardware architecture for efficient threshold-ordinal surface updates in event camera corner detection, significantly reducing latency and energy consumption on resource-limited edge devices.
Contribution
It proposes a novel near-memory architecture with optimized SRAM and power management techniques for fast, low-power corner detection in event-based cameras.
Findings
Reduces latency by up to 24.7x and energy by 1.2x at 1.2 V
Achieves robust circuit operation with minimal bit errors above 0.62 V
Maintains high corner detection accuracy with minor AUC reduction
Abstract
Event-based Cameras (EBCs) are widely utilized in surveillance and autonomous driving applications due to their high speed and low power consumption. Corners are essential low-level features in event-driven computer vision, and novel algorithms utilizing event-based representations, such as Threshold-Ordinal Surface (TOS), have been developed for corner detection. However, the implementation of these algorithms on resource-constrained edge devices is hindered by significant latency, undermining the advantages of EBCs. To address this challenge, a near-memory architecture for efficient TOS updates (NM-TOS) is proposed. This architecture employs a read-write decoupled 8T SRAM cell and optimizes patch update speed through pipelining. Hardware-software co-optimized peripheral circuits and dynamic voltage and frequency scaling (DVFS) enable power and latency reductions. Compared to…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Radiation Effects in Electronics · Low-power high-performance VLSI design
