Scalable Quantum Reversible BCD Adder Architectures with Enhanced Speed and Reduced Quantum Cost for Next-Generation Computing
Negin Mashayekhi, Mohammad Reza Reshadinezhad, Antonio Rubio, Shekoofeh Moghimi

TL;DR
This paper introduces scalable quantum reversible BCD adder architectures that significantly improve delay and quantum cost, supporting efficient next-generation quantum computing and arithmetic operations.
Contribution
It presents two novel reversible BCD adder designs optimized for delay and quantum cost, incorporating carry-skip techniques for enhanced performance.
Findings
Achieved up to 85.12% delay reduction
Reduced quantum cost by up to 30.75%
Demonstrated practical relevance with banking data analysis
Abstract
The quantum and reversible paradigm merges the principles of quantum mechanics and reversible computation to enable information-preserving processing. It supports next-generation computing architectures that provide improved scalability and enhanced computational efficiency. Within these architectures, the decimal adder is a key arithmetic component, particularly for Binary Coded Decimal (BCD) operations widely used in financial and commercial systems. However, most reversible BCD adders focus primarily on quantum and reversible metrics, overlooking the critical influence of delay, which makes balanced optimization a significant challenge. This paper presents two reversible BCD adder designs optimized for both delay and quantum cost. One design integrates the decimal carry-skip technique to improve the overall delay. Using reversible logic gates, the proposed architectures efficiently…
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Taxonomy
TopicsQuantum Computing Algorithms and Architecture · Cryptography and Residue Arithmetic · Quantum Information and Cryptography
