Leveraging Recurrent Patterns in Graph Accelerators

TL;DR

This paper introduces a novel graph processing method that leverages recurrent subgraph patterns to reduce memristor write operations, resulting in significant speed, energy efficiency, and circuit lifetime improvements in ReRAM-based graph accelerators.

Contribution

It proposes a static graph engine approach that minimizes reconfiguration by identifying frequent subgraphs, enhancing performance and durability over existing accelerators.

Findings

2.38x speedup over state-of-the-art accelerators

7.23x energy savings

2x circuit lifetime extension

Abstract

Graph accelerators have emerged as a promising solution for processing large-scale sparse graphs, leveraging the in-situ compu-tation of ReRAM-based crossbars to maximize computational efficiency. However, existing designs suffer from memristor access overhead due to the large number of graph partitions. This leads to increased execution time, higher energy consumption, and re-duced circuit lifetime. This paper proposes a graph processing method that minimizes memristor write operations by identifying frequent subgraph patterns and assigning them to graph engines, referred to as static, allowing most subgraphs to be processed without a need for crossbar reconfiguration. Experimental results show speed up to 2.38x speedup and 7.23x energy savings com-pared to state-of-the-art accelerators. Furthermore, our method extends the circuit lifetime by 2x compared to state-of-the-art ReRAM graph accelerators.