A WASM-Subset Stack Architecture for Low-cost FPGAs using Open-Source EDA Flows
Aradhya Chakrabarti (1) ((1) School of Computer Engineering, KIIT Deemed to be University)

TL;DR
This paper presents a low-cost, open-source FPGA microprocessor architecture based on a WASM-inspired ISA, optimized for resource constraints, and capable of executing simple applications with high code density and transparency.
Contribution
It introduces a novel dual-stack microprocessor design using a WASM subset ISA, synthesized with open-source tools for resource-constrained FPGAs, enabling transparent and portable deployment.
Findings
Achieved 27 MHz stable frequency on Gowin GW1NR-9 FPGA.
Implemented execution-in-place from SPI Flash to conserve Block RAM.
Demonstrated successful execution of simple calculator applications.
Abstract
Soft-core processors on resource-constrained FPGAs often suffer from low code density and reliance on proprietary toolchains. This paper details the design, implementation, and evaluation of a 32-bit dual-stack microprocessor architecture optimized for low-cost, resource-constrained Field-Programmable Gate Arrays (FPGAs). Implemented on the Gowin GW1NR-9 (Tang Nano 9K), the processor utilizes an instruction set architecture (ISA) inspired from a subset of the WebAssembly (WASM) specification to achieve high code density. Unlike traditional soft-cores that often rely on proprietary vendor toolchains and opaque IP blocks, this design is synthesized and routed utilizing an open-source flow, providing transparency and portability. The architecture features a dual-stack model (Data and Return), executing directly from SPI Flash via an Execute-in-Place (XIP) mechanism to conserve scarce Block…
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Taxonomy
TopicsEmbedded Systems Design Techniques · VLSI and FPGA Design Techniques · Parallel Computing and Optimization Techniques
