Efficient Kernel Mapping and Comprehensive System Evaluation of LLM Acceleration on a CGLA

TL;DR

This paper evaluates a flexible, non-AI-specific CGLA accelerator for LLMs, demonstrating significant energy efficiency improvements over GPUs and identifying data transfer as a key bottleneck for future design optimization.

Contribution

It provides the first comprehensive end-to-end evaluation of a CGLA accelerator for LLMs, highlighting its energy efficiency and flexibility compared to traditional GPU solutions.

Findings

Achieves up to 44.4x better Power-Delay Product than GPU

Reduces Energy-Delay Product by up to 11.5x compared to GPU

Identifies host-accelerator data transfer as a primary bottleneck

Abstract

Large Language Models (LLMs) demand substantial computational resources, resulting in high energy consumption on GPUs. To address this challenge, we focus on Coarse-Grained Reconfigurable Arrays (CGRAs) as an effective alternative that provides a trade-off between energy efficiency and programmability. This paper presents the first comprehensive, end-to-end evaluation of a non-AI-specialized Coarse-Grained Linear Array (CGLA) accelerator for the state-of-the-art Qwen LLM family. The architecture has a general-purpose, task-agnostic design, yet its flexible instruction set allows for domain-specific adaptations. This flexibility enables the architecture to achieve high efficiency for sustainable LLM inference. We assess the performance of our architecture on an FPGA prototype using the widely adopted llama.cpp framework. We then project its potential as a 28nm ASIC and compare it against a high-performance GPU (NVIDIA RTX 4090) and an edge AI device (NVIDIA Jetson AGX Orin). While GPUs exhibit lower latency, our non-AI-specific accelerator achieves higher energy efficiency, improving the Power-Delay Product (PDP) by up to 44.4x and 13.6x compared with the RTX 4090 and Jetson, respectively. Similarly, it reduces the Energy-Delay Product (EDP) by up to 11.5x compared to the high-performance GPU, demonstrating a favorable performance-energy trade-off. Critically, our system-level analysis identifies host-accelerator data transfer as the primary performance bottleneck, a factor often overlooked in kernel-level studies. These findings provide design guidance for next-generation LLM accelerators. This work validates CGRAs as a suitable platform for LLM inference in power-constrained environments, without being confined to specific algorithms.