From RISC-V Cores to Neuromorphic Arrays: A Tutorial on Building Scalable Digital Neuromorphic Processors

TL;DR

This tutorial explains how to design scalable digital neuromorphic processors starting from RISC-V cores, illustrating architectural evolution, software techniques, and trade-offs using the SENECA platform as an example.

Contribution

It provides a comprehensive, step-by-step architectural guide for building digital neuromorphic processors, synthesizing prior findings and focusing on design trade-offs and domain-specific acceleration.

Findings

Illustrates architectural evolution from RISC-V cores to neural processing elements

Discusses software techniques like spike grouping and event-driven convolution

Analyzes performance and energy trade-offs in neuromorphic processor design

Abstract

Digital neuromorphic processors are emerging as a promising computing substrate for low-power, always-on EdgeAI applications. In this tutorial paper, we outline the main architectural design principles behind fully digital neuromorphic processors and illustrate them using the SENECA platform as a running example. Starting from a flexible array of tiny RISC-V processing cores connected by a simple Network-on-Chip (NoC), we show how to progressively evolve the architecture: from a baseline event-driven implementation of fully connected networks, to versions with dedicated Neural Processing Elements (NPEs) and a loop controller that offloads fine-grained control from the general-purpose cores. Along the way, we discuss software and mapping techniques such as spike grouping, event-driven depth-first convolution for convolutional networks, and hard-attention style processing for high-resolution event-based vision. The focus is on architectural trade-offs, performance and energy bottlenecks, and on leveraging flexibility to incrementally add domain-specific acceleration. This paper assumes familiarity with basic neuromorphic concepts (spikes, event-driven computation, sparse activation) and deep neural network workloads. It does not present new experimental results; instead, it synthesizes and contextualizes findings previously reported in our SENECA publications to provide a coherent, step-by-step architectural perspective for students and practitioners who wish to design their own digital neuromorphic processors.