InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning

TL;DR

InF-ATPG introduces an advanced reinforcement learning-based ATPG framework that leverages circuit partitioning and enhanced graph neural networks to significantly improve test pattern generation efficiency and fault coverage in IC testing.

Contribution

The paper presents a novel FFR-driven ATPG method that integrates advanced circuit representation with reinforcement learning, addressing reward delay and circuit modeling issues in prior ML-based ATPG approaches.

Findings

Reduces backtracks by 55.06% compared to traditional methods.

Decreases backtracks by 38.31% relative to existing ML approaches.

Improves fault coverage in circuit testing.

Abstract

Automatic test pattern generation (ATPG) is a crucial process in integrated circuit (IC) design and testing, responsible for efficiently generating test patterns. As semiconductor technology progresses, traditional ATPG struggles with long execution times to achieve the expected fault coverage, which impacts the time-to-market of chips. Recent machine learning techniques, like reinforcement learning (RL) and graph neural networks (GNNs), show promise but face issues such as reward delay in RL models and inadequate circuit representation in GNN-based methods. In this paper, we propose InF-ATPG, an intelligent FFR-driven ATPG framework that overcomes these challenges by using advanced circuit representation to guide RL. By partitioning circuits into fanout-free regions (FFRs) and incorporating ATPG-specific features into a novel QGNN architecture, InF-ATPG enhances test pattern generation efficiency. Experimental results show InF-ATPG reduces backtracks by 55.06\% on average compared to traditional methods and 38.31\% compared to the machine learning approach, while also improving fault coverage.